Xilinx子分类
【Xilinx】最后发表: 2023-11-09 19:18:55 by Meelin |
【Zynq】最后发表: 2020-03-07 20:44:38 by xbs2023 |
【开发工具与评估板】最后发表: 2020-02-27 19:22:39 by xbs2020 |
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【 生态系统与中间件】最后发表: 2020-03-08 11:19:03 by xbs2023 |
【活动与其他】最后发表: 2020-02-27 18:34:33 by xbs2020 |
【硬件优化】最后发表: 2022-07-14 17:01:32 by 许林彬 |
【软件智能】最后发表: 2020-02-27 19:35:33 by xbs2020 |
Xilinx
标题  |
作者 | 查看/回复 | 最后发表 |
|---|---|---|---|
| Xilinx_EDK_MicroBlaze_教程（初级） | 100201452 | 1890/2 | 2017-08-09 21:42:12 by chenyifan |
| ibs文件与pkg | liujinpeng | 1446/0 | 2017-07-27 15:39:11 by liujinpeng |
| 提问：下面问题怎么解决 | module | 1331/0 | 2017-07-19 13:11:16 by module |
| rapidIO怎样选择相邻dual的时钟 | wxxhit | 1340/0 | 2017-07-10 15:47:10 by wxxhit |
| when i run the routing, the Vivado can not finish | youguhantan | 1865/0 | 2017-07-04 10:58:26 by youguhantan |
| XILINX产品需求供应 | penjun2008 | 1463/0 | 2017-07-03 14:01:45 by penjun2008 |
| 请教一个在线更新FPGA配置芯片内容的方法 | xilinx论坛 | 1476/1 | 2017-06-20 09:35:26 by fq2168 |
| VIVADO例化FIFO和RAM出现的告警 | juncai811 | 2232/0 | 2017-06-13 16:24:21 by juncai811 |
| leon3开发环境求助 | Archerlee | 1493/1 | 2017-05-31 10:46:38 by Archerlee |
| Modelsim闪退 | wudixiaodong | 1289/0 | 2017-05-06 16:11:24 by wudixiaodong |
| ISE 9.2，win7 64位安装 | wudixiaodong | 1629/1 | 2017-05-03 11:23:43 by wudixiaodong |
| 请教！ | durant123 | 1435/0 | 2017-04-29 15:32:08 by durant123 |
| XILINX 教程 | himalaya0604 | 1754/1 | 2017-04-28 15:59:59 by 叶子长新芽 |
| 求助Vivado里怎样修改IP核源代码 | 1253340505 | 7351/2 | 2017-04-21 09:33:28 by Novelty |
| 请教XILINX FIFO Generator中关于BACKUP的问题 | gxy670166755 | 1543/0 | 2017-04-13 16:00:22 by gxy670166755 |
| 寻求33.33MhzVCXO 1ppm 物料，方便请留下联系方式，谢谢！ | ypchenkelly | 1323/0 | 2017-03-29 12:44:37 by ypchenkelly |
| 请教一个vivado使用时一个奇怪的现象 | lg57708612 | 1753/0 | 2017-03-21 09:32:08 by lg57708612 |
| vivado去哪下载 | 刘海敏 | 1268/1 | 2017-03-19 20:55:39 by mycherrys9 |
| 关于使用VIVADO的仿真问题 | taoger | 1531/2 | 2017-03-06 15:55:31 by taoger |
| 关于vivado的综合问题 | 18463101022 | 1936/0 | 2017-03-06 10:28:08 by 18463101022 |
| vivado 程序有相应的 com/ole/activeX 程序访问进程吗？ | dinggaofei | 1328/0 | 2017-02-28 22:25:29 by dinggaofei |
| 求助各位大神！ 关于vivado HLS 硬件资源消耗 | sjtulzj | 1765/0 | 2017-01-16 22:27:31 by sjtulzj |
| pci核的例程是完整的吗？为什么下载进板子里检测不到pci设备呢？ | zhizihua209 | 1490/1 | 2017-01-12 12:18:38 by hubertli |
| 小白求助。ChipScope 仿真问题 | xiaochaohit | 1622/0 | 2017-01-09 19:25:27 by xiaochaohit |
| 求助各位大神！ethernet mac问题 | huhuyue045 | 1702/1 | 2016-12-28 13:51:03 by huhuyue045 |
| vivado 2016.3版本中mig编译失败的问题 | whubax | 3150/2 | 2016-12-21 21:58:12 by yypeng |
| PCI EXPRESS xilinx FPGA 教程 | 09120754 | 1665/2 | 2016-12-21 11:08:57 by anytao |
| uCOS_II在Microblaze平台上的移植 | toeflsieasy | 1395/2 | 2016-12-08 10:43:44 by wmltiger |
| zynq求教 | xiaowangdaxia | 1459/0 | 2016-12-06 13:29:08 by xiaowangdaxia |
| PL多个中断源如何链接到PS | xtihc2008 | 1511/2 | 2016-12-01 10:06:38 by xtihc2008 |
| Zynq-7020+AD9361的SIMULINK通信链路快速验证开发 | xuxuemingdw | 5722/0 | 2016-11-28 08:36:03 by xuxuemingdw |
| zynq烧录efuse提示线缆不兼容是什么意思？ | xiaolin4006 | 1386/0 | 2016-11-09 18:17:27 by xiaolin4006 |
| 通过赛灵思Virtex-7 产品系列以及高级综合实现TeraFLOP 性能 | xilinx论坛 | 1278/1 | 2016-11-09 10:20:44 by shaohaijun |
| virtex5 (xc5vlx50t)低温（-40度）PLL失锁的问题 | WangwpED | 2021/0 | 2016-10-26 08:59:04 by WangwpED |
| spartan6 pll 失锁问题 | xilinx论坛 | 1957/1 | 2016-10-26 08:43:42 by WangwpED |
| System Generator 生成的HDL代码使用ISE综合时出现错误 | deligent | 1799/0 | 2016-10-12 14:29:11 by deligent |
| axi_uartlite2.0中的例子文件如何修改，发一个Hello World!? | hawkgreen | 2465/0 | 2016-09-29 14:13:27 by hawkgreen |
| spartan6千兆以太网GMAC RGMII直连 | acan375 | 2166/0 | 2016-09-08 21:56:16 by acan375 |
| spartan6千兆以太网GMAC RGMII直连 | acan375 | 1874/0 | 2016-09-08 21:51:18 by acan375 |
| 全球首款同时同频全双工软件无线电平台 | xuxuemingdw | 1866/0 | 2016-09-01 17:33:57 by xuxuemingdw |