Xilinx子分类
【Xilinx】最后发表: 2023-11-09 19:18:55 by Meelin |
【Zynq】最后发表: 2020-03-07 20:44:38 by xbs2023 |
【开发工具与评估板】最后发表: 2020-02-27 19:22:39 by xbs2020 |
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【 生态系统与中间件】最后发表: 2020-03-08 11:19:03 by xbs2023 |
【活动与其他】最后发表: 2020-02-27 18:34:33 by xbs2020 |
【硬件优化】最后发表: 2022-07-14 17:01:32 by 许林彬 |
【软件智能】最后发表: 2020-02-27 19:35:33 by xbs2020 |
Xilinx
标题  |
作者 | 查看/回复 | 最后发表 |
|---|---|---|---|
| 求各位大神指导，xps_ll_demac IP核在ISE14.7系统下的license问题 | dgsds浩 | 1436/0 | 2015-10-20 15:20:50 by dgsds浩 |
| xilinx逻辑分析仪chipscope抓取信号问题 | czh306 | 2262/2 | 2015-10-20 14:42:55 by Congle |
| Virtex-6（ML605）板子配置千兆以太网，请指教！ | xilinx论坛 | 2794/2 | 2015-10-12 22:27:08 by huangww79 |
| serdes , xilinx GTX IP ,simulation,仿真问题 | czh306 | 1800/1 | 2015-10-12 22:21:44 by huangww79 |
| xilinx sdk中编译程序报undefined reference to 'sin'错误，请问怎么解决？谢谢 | gpszseu | 4690/3 | 2015-09-29 15:20:47 by mingnice |
| Xilinx SDK编译报错undefined reference to ‘log’ | mingnice | 2841/4 | 2015-09-29 15:16:52 by mingnice |
| V7和PROM JTAG链接顺序对VIVADO的影响，求解各位大神 | XILINX雷科 | 1750/0 | 2015-09-24 09:44:40 by XILINX雷科 |
| vivado如何在不重新实现的情况下更新rom中的初始化coe数据？ | shixue | 3996/0 | 2015-09-22 10:42:55 by shixue |
| 三重好礼，热辣来袭！Vivado进阶之路现已开启！ | nakey | 7699/8 | 2015-09-16 01:38:36 by philip01 |
| 关于跑综合等工程的服务器？？？大概要多少钱？哪种好？ | pilishen | 1706/0 | 2015-09-11 19:26:40 by pilishen |
| xilinx FPGA 中GTX或GTP可否级联？ | toeflsieasy | 1562/2 | 2015-09-07 15:15:13 by ctc235000 |
| Xilinx Virtex-6 FPGA ML605开发评估方案 | 09120578 | 1393/1 | 2015-09-07 15:14:38 by ctc235000 |
| Xilinx FPGA DCI的应用 | 09120578 | 1576/1 | 2015-09-07 15:14:10 by ctc235000 |
| 请教xilinx selectmap配置失败原因？ | czh306 | 2446/1 | 2015-09-07 15:13:45 by ctc235000 |
| xilinx v5系列 硬核使用指南 | himalaya0604 | 2455/1 | 2015-09-07 15:13:14 by ctc235000 |
| SPARTAN6的硬核DDR控制器能不能交换数据脚 | 天才少年 | 1523/1 | 2015-09-07 15:12:42 by ctc235000 |
| 请教一下关于xilinx fir compiler中差分输出的问题 | himalaya0604 | 1473/1 | 2015-09-07 15:11:50 by ctc235000 |
| CTC集团中国代表处 提供xilinx FPGA | ctc235000 | 2209/0 | 2015-09-07 15:06:46 by ctc235000 |
| 哪些器件会造成adc采集有噪声 | 18782458718 | 1901/0 | 2015-08-28 17:28:23 by 18782458718 |
| 向xilinx v7系列fpga的BPI flash中下载程序的问题 | hutushenxinxin | 1829/0 | 2015-08-26 15:39:41 by hutushenxinxin |
| XILINX Device Constraints Guid | himalaya0604 | 1316/0 | 2015-08-10 23:16:31 by himalaya0604 |
| 在用xilinx SDK时，有时会出现莫名奇妙的问题 | himalaya0604 | 1665/0 | 2015-08-10 23:11:28 by himalaya0604 |
| xilinx V6 FPGA PCB设计指导 | himalaya0604 | 1377/0 | 2015-08-10 23:10:07 by himalaya0604 |
| xilinx fpga内部信号线的延时约束 | himalaya0604 | 1473/0 | 2015-08-09 23:22:46 by himalaya0604 |
| Xilinx浮点转换Matlab界面 | himalaya0604 | 1454/0 | 2015-08-09 21:21:07 by himalaya0604 |
| fpga控制sata 接口硬盘进行数据存取 Gbps | himalaya0604 | 1543/0 | 2015-08-09 21:19:38 by himalaya0604 |
| 终极参考，how to use xilinx core generator | czh306 | 1297/0 | 2015-08-07 23:13:24 by czh306 |
| verilog 写的交通灯程序，可综合实现的！ | czh306 | 1230/0 | 2015-08-07 23:10:01 by czh306 |
| Calibration of DAC from XILINX | czh306 | 1306/0 | 2015-08-07 23:06:04 by czh306 |
| 怎么用Verilog实现这样的时序呢 | 09120578 | 2035/0 | 2015-08-06 23:08:05 by 09120578 |
| xilinx journal | 09120578 | 1283/0 | 2015-08-06 23:00:49 by 09120578 |
| 我做的玩具 MIPS 2000 Core in Verilog | 09120578 | 1423/0 | 2015-08-06 22:56:51 by 09120578 |
| 一个有关Xilinx microblaze简单语法的问题 | 09120578 | 1414/0 | 2015-08-06 22:54:14 by 09120578 |
| “Double Nibble Detect”相关问题 | 唐山 | 1549/0 | 2015-08-06 14:07:29 by 唐山 |
| FPGA开发板上的CPLD怎样恢复默认配置？初学菜鸟求助！ | SCOFEEL | 1356/0 | 2015-08-05 23:40:40 by SCOFEEL |
| Xilinx的FPGA设计全流程 | toeflsieasy | 1476/0 | 2015-08-05 23:29:01 by toeflsieasy |
| 配置快速入门指南 | himalaya0604 | 1463/0 | 2015-08-05 23:10:36 by himalaya0604 |
| Xilinx ISE 9 深入辅导资料 | himalaya0604 | 1341/0 | 2015-08-05 23:08:59 by himalaya0604 |
| xilinx tri_EMAC核的一些细节问题 | toeflsieasy | 1453/0 | 2015-08-04 23:00:48 by toeflsieasy |
| 关于XILINX FPGA中VRP/VRN管脚的使用 | toeflsieasy | 2286/0 | 2015-08-04 23:00:10 by toeflsieasy |