Xilinx子分类
【Xilinx】最后发表: 2023-11-09 19:18:55 by Meelin |
【Zynq】最后发表: 2020-03-07 20:44:38 by xbs2023 |
【开发工具与评估板】最后发表: 2020-02-27 19:22:39 by xbs2020 |
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【 生态系统与中间件】最后发表: 2020-03-08 11:19:03 by xbs2023 |
【活动与其他】最后发表: 2020-02-27 18:34:33 by xbs2020 |
【硬件优化】最后发表: 2022-07-14 17:01:32 by 许林彬 |
【软件智能】最后发表: 2020-02-27 19:35:33 by xbs2020 |
Xilinx
标题  |
作者 | 查看/回复 | 最后发表 |
|---|---|---|---|
| 请教如何正确给FPGA的输入时钟和输出时钟分配引脚 | caonimab | 1699/1 | 2015-07-15 23:11:51 by 09120581 |
| vivado能识别ise综合生成的网表文件.ngc的吗？ | zxzzy2009 | 1911/0 | 2015-07-15 22:50:33 by zxzzy2009 |
| 基于Xilinx Zynq的物距测量系统设计与实现 | zxzzy2009 | 1710/0 | 2015-07-15 22:34:46 by zxzzy2009 |
| ADAS和通向无人驾驶汽车之路 | zxzzy2009 | 1299/0 | 2015-07-15 22:17:53 by zxzzy2009 |
| 7系列iodelay与Virtex-5的iodelay结构 | himalaya0604 | 1475/1 | 2015-07-14 22:58:05 by czh306 |
| zynq从SD卡启动Linux失败 | himalaya0604 | 1707/1 | 2015-07-14 22:57:46 by czh306 |
| Virtex-6（ML605）板子配置千兆以太网，请指教！ | himalaya0604 | 1452/1 | 2015-07-14 22:57:11 by czh306 |
| 使用ac97实现音频回环问题 | himalaya0604 | 1375/0 | 2015-07-14 22:17:23 by himalaya0604 |
| 如何通过ethernet连接两块或多块fpga数据传输 | himalaya0604 | 1300/0 | 2015-07-14 22:15:52 by himalaya0604 |
| SDK PS initialization failed | toeflsieasy | 2231/1 | 2015-07-13 23:15:07 by toeflsieasy |
| zc702 devicetree問題 | jjjjjjjjkkk | 1393/1 | 2015-07-13 23:14:50 by toeflsieasy |
| 高速ADC 数据接收 | jjjjjjjjkkk | 1334/1 | 2015-07-13 23:14:30 by toeflsieasy |
| 关于z7与cameralink full的对接 | jjjjjjjjkkk | 1612/1 | 2015-07-13 23:14:17 by toeflsieasy |
| 用MIG为A7 XC7A75T fpga 生成ddr3 IP核的问题 | jjjjjjjjkkk | 1563/1 | 2015-07-13 23:13:23 by toeflsieasy |
| V6和K7的RAPID IO传数问题 | jjjjjjjjkkk | 1559/0 | 2015-07-13 22:33:27 by jjjjjjjjkkk |
| 关于xlinx sprtan-6 系列FPGA XC6SLX9-2TQG144C 时钟和 PLL 问题 | lilianhu | 5955/0 | 2015-07-12 22:54:32 by lilianhu |
| xc95144xl -5tq100复位信号问题 | lilianhu | 7240/0 | 2015-07-12 22:51:19 by lilianhu |
| Question about Kintex-7 HR bank LVDS bus | lilianhu | 1618/0 | 2015-07-12 22:36:07 by lilianhu |
| Virtex 7 VC709 与 Spantan6 Aurora 连接问题 | lilianhu | 1512/0 | 2015-07-12 22:35:13 by lilianhu |
| 如何使CPLD引脚输出高阻状态 | lilianhu | 1296/0 | 2015-07-12 22:13:38 by lilianhu |
| 用Tcl定制Vivado设计实现流程 | xilinx论坛 | 1607/0 | 2015-07-11 23:06:46 by xilinx论坛 |
| 像app一样下载使用Tcl脚本－Xilinx推出Tcl Store脚本库 | xilinx论坛 | 1337/0 | 2015-07-11 23:02:24 by xilinx论坛 |
| XDC约束技巧之I/O篇 (下) | xilinx论坛 | 2503/0 | 2015-07-11 22:52:45 by xilinx论坛 |
| XDC约束技巧之I/O篇 (上) | xilinx论坛 | 1858/0 | 2015-07-11 22:52:23 by xilinx论坛 |
| XDC约束技巧——时钟篇 [ | xilinx论坛 | 3648/0 | 2015-07-11 22:18:45 by xilinx论坛 |
| 【Vivado使用误区与进阶】读懂用好 Timing Report [ | xilinx论坛 | 1990/0 | 2015-07-11 22:00:46 by xilinx论坛 |
| define_attribute {n:top.data[31:0]} {syn_keep} {"true"} define_attribute {n:top. | xilinx论坛 | 9664/0 | 2015-07-11 21:53:34 by xilinx论坛 |
| V6 关于selectIO的使用 | xilinx论坛 | 1331/0 | 2015-07-10 22:33:05 by xilinx论坛 |
| v6 ISERDES 的时钟使能信号CE1CE2能否作为输入输出时序控制 | xilinx论坛 | 6187/0 | 2015-07-10 22:17:00 by xilinx论坛 |
| 求助xilinx virtex-6电源问题 | xilinx论坛 | 1289/0 | 2015-07-10 22:14:17 by xilinx论坛 |
| 求助，spartan-6 JTAG下不进去程序 | xilinx论坛 | 2113/0 | 2015-07-10 22:12:52 by xilinx论坛 |
| vivado 设计CPU | 09120578 | 1330/0 | 2015-07-09 23:17:47 by 09120578 |
| Partial Reconfiguration using HWICAP not responding | himalaya0604 | 1356/0 | 2015-07-09 22:46:33 by himalaya0604 |
| 关于ICAP的使用问题 | himalaya0604 | 1252/0 | 2015-07-09 22:38:17 by himalaya0604 |
| 求助关于BASYS2板子连接的问题 | himalaya0604 | 1370/0 | 2015-07-09 22:20:21 by himalaya0604 |
| 在ISE中，可否将8个ROM合并成一个ROM元件？ | himalaya0604 | 1292/0 | 2015-07-09 22:19:28 by himalaya0604 |
| xqr4vsx55里没有MIG核，可以用xc4vsx55生成的MIG核代替吗 | xilinx论坛 | 1235/0 | 2015-07-08 18:47:23 by xilinx论坛 |
| sdk 代码优化 | xilinx论坛 | 1542/0 | 2015-07-08 18:45:44 by xilinx论坛 |
| 关于central interconnect的burst功能 | xilinx论坛 | 4507/0 | 2015-07-08 18:45:04 by xilinx论坛 |
| XC706 - 如何脱离里开发环境sdk运行 | xilinx论坛 | 1421/0 | 2015-07-08 18:44:40 by xilinx论坛 |