Xilinx子分类
【Xilinx】最后发表: 2023-11-09 19:18:55 by Meelin |
【Zynq】最后发表: 2020-03-07 20:44:38 by xbs2023 |
【开发工具与评估板】最后发表: 2020-02-27 19:22:39 by xbs2020 |
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【 生态系统与中间件】最后发表: 2020-03-08 11:19:03 by xbs2023 |
【活动与其他】最后发表: 2020-02-27 18:34:33 by xbs2020 |
【硬件优化】最后发表: 2022-07-14 17:01:32 by 许林彬 |
【软件智能】最后发表: 2020-02-27 19:35:33 by xbs2020 |
Xilinx
标题  |
作者 | 查看/回复 | 最后发表 |
|---|---|---|---|
| 用 Xilinx CPLD 与 NAND Flash 存储器器件接口 | Rancho | 1646/1 | 2012-05-25 12:25:45 by h254479169 |
| FIR Compiler IP Core问题求助 | wwmumu | 7640/18 | 2012-05-20 11:13:33 by pengyanyun |
| FPGA实现高清信号的实时解码 | winthony | 1446/0 | 2012-05-17 16:15:23 by winthony |
| 为什么Xilinx器件中BRAM大小是18K？ | jhp79 | 1665/0 | 2012-05-16 12:18:45 by jhp79 |
| 小调查：你对下面哪些FPGA器件感兴趣？ | lemonsky | 1695/5 | 2012-05-16 08:59:24 by xtqxtq1111 |
| Vivado 赛灵思最新设计开发套件 | winthony | 1422/0 | 2012-05-15 11:35:20 by winthony |
| 高效的移位寄存器、LFSR 计数器和长伪随机序列发生器 | Rancho | 1530/0 | 2012-05-13 09:55:33 by Rancho |
| 将 DDR SDRAM 与 CoolRunner-II CPLD 接口 | Rancho | 1384/0 | 2012-05-13 09:52:30 by Rancho |
| 利用 CoolRunner-II CPLD 和 SPI 闪存配置 Xilinx FPGA | Rancho | 1490/0 | 2012-05-13 09:51:39 by Rancho |
| 无需板仿真即可估计实际的输出时序 | Rancho | 1323/0 | 2012-05-13 09:50:54 by Rancho |
| 133 MHz PCI-X 到128 MB DDR 小型 DIMM 存储器桥 | Rancho | 1272/0 | 2012-05-13 09:50:07 by Rancho |
| Virtex-5 系列高级封装 | Rancho | 1264/0 | 2012-05-13 09:49:20 by Rancho |
| 单纠错和双检错（中文版） | Rancho | 1375/0 | 2012-05-13 09:47:26 by Rancho |
| 利用 Virtex-4 器件实现 QDR II SRAM 接口（中文版） | Rancho | 1534/0 | 2012-05-13 09:46:27 by Rancho |
| 使用 Virtex-4 FPGA 器件实现 DDR SDRAM 控制器（中文版） | Rancho | 1554/0 | 2012-05-13 09:45:31 by Rancho |
| 利用 Xilinx FPGA 和存储器接口生成器简化存储器接口（中文版） | Rancho | 1364/0 | 2012-05-13 09:44:38 by Rancho |
| 将 64 位 DDR 存储器总线与 32 位微处理器总线接口 | Rancho | 1410/0 | 2012-05-13 09:43:31 by Rancho |
| 使用 ISERDES 和 OSERDES 实现高性能 DDR2 SDRAM 接口数据采集 | Rancho | 1788/0 | 2012-05-13 09:42:27 by Rancho |
| 利用直接时钟控制技术实现 DDR2 SDRAM 物理层 | Rancho | 1347/0 | 2012-05-13 09:41:31 by Rancho |
| 用于实现 RAID6 奇偶性的硬件加速器 | Rancho | 1326/0 | 2012-05-13 09:40:44 by Rancho |
| 存储器接口应用指南概述 | Rancho | 1267/0 | 2012-05-13 09:39:50 by Rancho |
| 面向 Virtex-4 FPGA 的可综合 CIO DDR RLDRAM II 控制器 | Rancho | 1179/0 | 2012-05-13 09:38:59 by Rancho |
| 更宽的块存储器 | Rancho | 1216/0 | 2012-05-13 09:37:36 by Rancho |
| XAPP702 - 使用 Virtex-4 器件实现 DDR2 控制器 | Rancho | 1192/0 | 2012-05-13 09:36:50 by Rancho |
| 面向Virtex™-II Pro FPGA的DDR2 SDRAM存储器接口 | Rancho | 1412/0 | 2012-05-13 09:35:44 by Rancho |
| 用于 RAID6 奇偶生成/数据恢复控制器的硬件加速器 | Rancho | 1244/0 | 2012-05-13 09:34:57 by Rancho |
| Using Digitally Controlled Impedance: Signal Integrity vs Power Dissipation Cons | Rancho | 1892/0 | 2012-05-13 09:33:38 by Rancho |
| 参考设计：带有 OPB 中心 DMA 的 MCH OPB EMC | Rancho | 1161/0 | 2012-05-13 09:31:36 by Rancho |
| 参考系统：带有 OPB 中心 DMA 的 PLB DDR2 | Rancho | 1334/0 | 2012-05-13 09:30:42 by Rancho |
| 从配置 PROM 读取用户数据 | Rancho | 1192/0 | 2012-05-13 09:29:46 by Rancho |
| 在 Spartan-3A FPGA 内实现 DDR2-400 存储器接口 | Rancho | 1565/0 | 2012-05-13 09:28:54 by Rancho |
| 使用 Virtex-4 器件的 DDR2 控制器（267 MHz 及以上） | Rancho | 1142/0 | 2012-05-13 09:27:45 by Rancho |
| Virtex-5 FPGAs RLDRAM II 寄存器接口 | Rancho | 1341/0 | 2012-05-13 09:26:55 by Rancho |
| Accelerating System Designs Requiring High-Bandwidth Connectivity with Targeted | Rancho | 1288/0 | 2012-05-13 09:26:06 by Rancho |
| High-Performance DDR2 SDRAM Interface in Virtex-5 Devices | Rancho | 1290/0 | 2012-05-13 09:25:10 by Rancho |
| The purpose of this white paper is to describe how Spartan®-6 FPGAs address the | Rancho | 1157/0 | 2012-05-13 09:24:03 by Rancho |
| Virtex 器件中的多个 CAM 设计概述 | Rancho | 1255/0 | 2012-05-13 09:16:50 by Rancho |
| Parameterizable LocalLink FIFO - Not Recommended for New Designs | Rancho | 1282/0 | 2012-05-13 09:15:47 by Rancho |
| Self-Addressing FIFO | Rancho | 1346/0 | 2012-05-13 09:14:58 by Rancho |
| FIFOs Using Virtex-II Block RAM - Obsolete | Rancho | 1293/0 | 2012-05-13 09:14:11 by Rancho |