Xilinx子分类
【Xilinx】最后发表: 2023-11-09 19:18:55 by Meelin |
【Zynq】最后发表: 2020-03-07 20:44:38 by xbs2023 |
【开发工具与评估板】最后发表: 2020-02-27 19:22:39 by xbs2020 |
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【 生态系统与中间件】最后发表: 2020-03-08 11:19:03 by xbs2023 |
【活动与其他】最后发表: 2020-02-27 18:34:33 by xbs2020 |
【硬件优化】最后发表: 2022-07-14 17:01:32 by 许林彬 |
【软件智能】最后发表: 2020-02-27 19:35:33 by xbs2020 |
Xilinx
标题  |
作者 | 查看/回复 | 最后发表 |
|---|---|---|---|
| 关于HDL数学函数实现的设计技巧 | Rancho | 1320/0 | 2012-05-08 17:00:51 by Rancho |
| 为Spartan-6 FPGAs定位并重新定位目标指南 | Rancho | 1220/0 | 2012-05-08 16:56:45 by Rancho |
| Virtex-5 FPGA 六输入 LUT 架构的优势（中文版） | Rancho | 1475/0 | 2012-05-08 16:54:48 by Rancho |
| 利用 SRL16E 节省成本 | Rancho | 1141/0 | 2012-05-08 16:54:15 by Rancho |
| 有以下几个问题请斑主解答,谢谢 | inlaid | 3111/7 | 2012-05-08 08:59:43 by fenglema |
| CoolRunner-II 演示板 | Rancho | 1275/0 | 2012-05-07 19:44:47 by Rancho |
| XC9500XL CPLD 上电顺序与热插拔 | Rancho | 1316/0 | 2012-05-07 19:44:01 by Rancho |
| 了解 CoolRunner-II 时序模型 | Rancho | 1318/0 | 2012-05-07 19:43:16 by Rancho |
| 使用 XC9500XL 时序模型 | Rancho | 1206/0 | 2012-05-07 19:42:49 by Rancho |
| 使用 XC9500 时序模型 | Rancho | 1250/0 | 2012-05-07 19:42:23 by Rancho |
| 使用 CoolRunner XPLA3 时序模型 | Rancho | 1258/0 | 2012-05-07 19:41:53 by Rancho |
| CoolRunner XPLA3 时钟选项 | Rancho | 1310/0 | 2012-05-07 19:41:23 by Rancho |
| DataGATE 和“休眠模式”的差异 | Rancho | 1024/0 | 2012-05-07 19:40:37 by Rancho |
| 使用非标准电压给 CoolRunner-II CPLD 供电 | Rancho | 1151/0 | 2012-05-07 19:40:08 by Rancho |
| CoolRunner-II DataGATE的实际价值 | Rancho | 1250/0 | 2012-05-07 19:39:40 by Rancho |
| 用 Xilinx CPLD 实现 TTL 功能时的资源占用率 | Rancho | 1182/0 | 2012-05-07 19:39:07 by Rancho |
| 从分立 7400 逻辑器件转向到 CPLD 的优势 | Rancho | 1033/0 | 2012-05-07 19:38:38 by Rancho |
| CoolRunner-II 真正数字化技术 | Rancho | 1431/0 | 2012-05-07 19:38:01 by Rancho |
| CoolRunner-II CPLDs 在安全上应用 | Rancho | 1376/0 | 2012-05-07 19:36:42 by Rancho |
| 利用 XCF32P Platform Flash PROM 简化在系统编程 | Rancho | 1371/0 | 2012-05-07 19:34:46 by Rancho |
| 针对 Xilinx 器件的 SVF 和 XSVF 文件格式 | Rancho | 1644/0 | 2012-05-07 19:34:17 by Rancho |
| J 驱动：IEEE 标准 1532 器件的在系统 (In-System) 编程 | Rancho | 1412/0 | 2012-05-07 19:33:45 by Rancho |
| 嵌入式 JTAG ACE 播放器 | Rancho | 1116/0 | 2012-05-07 19:33:18 by Rancho |
| 利用边界扫描来实现 Spartan-II 和 Spartan-IIE FPGA 的配置和读回 | Rancho | 1304/0 | 2012-05-07 19:32:50 by Rancho |
| 快速 JTAG ISP 列表 | Rancho | 1287/0 | 2012-05-07 19:32:18 by Rancho |
| 在边界扫描系统中利用在系统编程 | Rancho | 1420/0 | 2012-05-07 19:31:42 by Rancho |
| 使用 XC9500 JTAG 边界扫描接口 | Rancho | 1269/0 | 2012-05-07 19:31:12 by Rancho |
| 使用串行矢量格式文件对 XC9500 器件进行在系统编程 | Rancho | 1208/0 | 2012-05-07 19:30:42 by Rancho |
| Xilinx 内嵌系统编程使用了一个嵌入式微控制器 | Rancho | 1227/0 | 2012-05-07 19:30:13 by Rancho |
| XC4000/XC5200 器件内的边界扫描 | Rancho | 1204/0 | 2012-05-07 19:27:58 by Rancho |
| 使用 XC9500XL CPLD 进行设计 | Rancho | 1163/0 | 2012-05-07 19:26:47 by Rancho |
| 使用 XPLA3 通用控制术语 | Rancho | 1221/0 | 2012-05-07 19:26:13 by Rancho |
| CPLD 多电压系统设计 | Rancho | 1069/0 | 2012-05-07 19:25:41 by Rancho |
| CoolRunner XPLA3 CPLD 的宏单元配置 | Rancho | 1273/0 | 2012-05-07 19:25:10 by Rancho |
| 利用 Verilog 来创建 CPLD 设计 | Rancho | 1280/0 | 2012-05-07 19:23:52 by Rancho |
| CPLD VHDL 介绍 | Rancho | 1284/0 | 2012-05-07 19:23:28 by Rancho |
| 了解 CoolRunner-II 逻辑引擎 | Rancho | 1266/0 | 2012-05-07 19:22:57 by Rancho |
| IBM 特许 Xilinx 嵌入式 FPGA 核用于 SoC ASIC | Rancho | 1284/0 | 2012-05-07 19:22:26 by Rancho |
| 汽车处理器被淘汰成为历史吗? | Rancho | 1178/0 | 2012-05-07 19:21:53 by Rancho |
| 远程信息处理数字融合：如何应对新兴标准和协议 | Rancho | 1369/0 | 2012-05-07 19:20:06 by Rancho |