【Xilinx】最后发表: 2023-11-09 19:18:55 by Meelin |
【Zynq】最后发表: 2020-03-07 20:44:38 by xbs2023 |
【开发工具与评估板】最后发表: 2020-02-27 19:22:39 by xbs2020 |
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【 生态系统与中间件】最后发表: 2020-03-08 11:19:03 by xbs2023 |
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【硬件优化】最后发表: 2022-07-14 17:01:32 by 许林彬 |
【软件智能】最后发表: 2020-02-27 19:35:33 by xbs2020 |
标题 ![]() |
作者 | 查看/回复 | 最后发表 |
|---|---|---|---|
| 求助:ERROR:Place:864 - Incompatible IOB's are locked to the same bank 3 | toeflsieasy | 2391/0 | 2015-04-19 11:22:59 by toeflsieasy |
| 如何选择合适的FPGA千兆位收发器? | toeflsieasy | 1003/0 | 2015-04-19 11:21:26 by toeflsieasy |
| 求助:关于应用笔记xapp224_data recovery | toeflsieasy | 1252/0 | 2015-04-19 11:20:00 by toeflsieasy |
| DSO “comparo”彰显先进的Smarter System | SCOFEEL | 1061/0 | 2015-04-18 23:57:48 by SCOFEEL |
| 回到未来:用图形化方法快速实现复杂的SoC设计 | iamacb1 | 1057/0 | 2015-04-18 23:53:21 by iamacb1 |
| 打造安全的嵌入式系统至关重要 | iamacb1 | 912/0 | 2015-04-18 23:47:42 by iamacb1 |
| 关于V5器件差分接口的一些疑问? | iamacb1 | 925/0 | 2015-04-18 23:46:42 by iamacb1 |
| 怎么申请 调试版本 以太网络license | a6251356 | 859/0 | 2015-04-18 00:07:57 by a6251356 |
| 使用XILINX FPGA实现的SATA硬盘控制和高速存储 | muzhen2000 | 1009/0 | 2015-04-18 00:05:25 by muzhen2000 |
| 问题求助?Verilog例化ODDR2时报错 | muzhen2000 | 1519/0 | 2015-04-17 23:25:16 by muzhen2000 |
| lwip在xc3s700an上应用时只使用BRAM资源是否足够 | muzhen2000 | 1076/0 | 2015-04-17 23:24:17 by muzhen2000 |
| [求助]Master and Slave R/W address problem .About the three of Processing System(P | muzhen2000 | 1191/0 | 2015-04-17 23:22:43 by muzhen2000 |
| 怎么把用户逻辑V文件翻译成FPGA内部原件的V文件??? | 2007zoz | 1016/0 | 2015-04-17 23:21:28 by 2007zoz |
| 求助:关于EDK 下利用LWIP实现双网口 | 2007zoz | 1156/0 | 2015-04-17 23:19:58 by 2007zoz |
| 关于使用clocking wizard 的询问? | 2007zoz | 1270/0 | 2015-04-17 23:18:39 by 2007zoz |
| where can find the third part programmer qualified by xilinx liset | 2007zoz | 1061/0 | 2015-04-17 23:17:35 by 2007zoz |
| Xilinx 推出全新的 FPGA 设计方法培训课程 | 2007zoz | 943/0 | 2015-04-17 23:16:37 by 2007zoz |
| 把握赛灵思FPGA中的主要时钟资源 (作者:Sharad Sinha 新加坡南洋理工大学博士生) | 091217272 | 1552/0 | 2015-04-16 00:15:30 by 091217272 |
| 最新的vertex5 ug190中DCM、PLL的几个时序图难理解! | 091217272 | 964/0 | 2015-04-16 00:14:26 by 091217272 |
| 请教如何正确给FPGA的输入时钟和输出时钟分配引脚 | 091217272 | 1011/0 | 2015-04-16 00:13:38 by 091217272 |
| 关于比特流下载出错的问题:Device IDCODE不正确,全是0. | abgh668 | 924/0 | 2015-04-16 00:12:29 by abgh668 |
| Data2MEM:47 - Not all BitLanes in ADDRESS_SPACE | abgh668 | 2904/0 | 2015-04-16 00:11:15 by abgh668 |
| 用spartan6实现SATA接口的试种恢复问题 | abgh668 | 1061/0 | 2015-04-16 00:05:11 by abgh668 |
| 如何正确使用FPGA的时钟资源 | abgh668 | 927/0 | 2015-04-16 00:01:11 by abgh668 |
| FPGA工程师手记:FPGA系统设计黄金法则 (转自OFweek电子工程网) | tuozi241 | 1069/0 | 2015-04-12 22:56:42 by tuozi241 |
| V5输入信号怎么会被弄到IODELAY模块里过了一圈呢? | tuozi241 | 1065/0 | 2015-04-12 22:55:22 by tuozi241 |
| EDK14.4 MicroBlaze如何从Flash启动? | tuozi241 | 960/0 | 2015-04-12 22:54:40 by tuozi241 |
| (求助)PLL输入时钟抖动,导致PLL不工作 | tuozi241 | 997/0 | 2015-04-12 22:54:01 by tuozi241 |
| 用V7GTH的自驱动能力简化评估链路性能 | tuozi241 | 1138/0 | 2015-04-12 22:53:19 by tuozi241 |
| 如何阻止综合工具综合掉相同的例化模块 | tuozi241 | 937/0 | 2015-04-12 22:52:20 by tuozi241 |
| 【求助】硬件实现协议卸载 | pengrui | 1030/0 | 2015-04-12 21:29:10 by pengrui |
| 一种多芯片串行收发器纠偏方法 | pengrui | 1056/0 | 2015-04-12 21:26:57 by pengrui |
| 图中为XC95144XL,pin_locking capability指的是什么? | pengrui | 913/0 | 2015-04-12 21:25:29 by pengrui |
| LWIP “Temac error interrupt: Rx fifo over run”,使用V5_TEMAC_IP打印信息报错求助? | pengrui | 1258/0 | 2015-04-12 21:24:36 by pengrui |
| SFP+光模块接口设计调试优化方法 | pengrui | 1400/0 | 2015-04-12 21:23:55 by pengrui |
| Xilinx专家秘笈分享连载- 1-15 | zxzzy2009 | 1103/0 | 2015-04-12 21:22:43 by zxzzy2009 |
| matlab下使用System generator出现undriven input port? "Error reported by S-function 's | zxzzy2009 | 1844/0 | 2015-04-12 21:21:52 by zxzzy2009 |
| Virtex5系列FPGA上电瞬间IO状态 | zxzzy2009 | 991/0 | 2015-04-12 21:20:57 by zxzzy2009 |
| simulink中打不开SysytemGenerator?返回错误Error evaluating 'OpenFcn' callback of Xilinx S | zxzzy2009 | 2420/0 | 2015-04-12 21:20:17 by zxzzy2009 |
| Xilinx与台积公司宣布:全线量产采用CoWoSTM技术的28nm All Programmable 3D IC系列 | zxzzy2009 | 1071/0 | 2015-04-12 21:19:14 by zxzzy2009 |