这是我用verilog例化的oddr2

ODDR2 TX0               (     

.Q(TXD[0]),               

.D0(gtx_low[0]),          

.D1(gtx_high[0]),         

.C0(NO_TXCLK),      

  .C1(TXCLK),    

.CE(1'b1),            

.R(1'b0),               

.S(1'b0)           

);              

但是会报错：

Pack:2531 - The dual data rate register "rgmii2gmii/TX0" failed to join    the "OLOGIC2" component as required.  The output signal for register symbol rgmii2gmii/TX0 requires general routing to fabric, but the register can only    be routed to ILOGIC, IODELAY, and IOB.

该怎么解决?

这个是RGMII转GMII处理中例化ODDR2出现的问题。