Xilinx|
版主: 51FPGA Q & A |
Xilinx
标题  |
作者 | 查看/回复 | 最后发表 |
|---|---|---|---|
| 低成本超声波 | inrxkj | 1197/0 | 2015-07-19 18:19:15 by inrxkj |
| 清除通向基于FPGA的OpenCL数据中心服务器的障碍 | sydfeng | 1182/0 | 2015-07-18 23:04:05 by sydfeng |
| 使用FPGA优化视频水印操作的OpenCL应用 | sydfeng | 1271/0 | 2015-07-18 22:28:42 by sydfeng |
| 全面掌控频域 | toeflsieasy | 1272/0 | 2015-07-18 22:21:37 by toeflsieasy |
| 将SoC平台设计与DSP系统生成器相集成 | toeflsieasy | 1283/0 | 2015-07-18 22:02:32 by toeflsieasy |
| 重新思考快速宽频ADC中的数字下变频 | toeflsieasy | 1387/0 | 2015-07-18 22:01:52 by toeflsieasy |
| 基于basys2的投影键盘——项目进度记录第一天 | toeflsieasy | 1321/0 | 2015-07-18 22:00:22 by toeflsieasy |
| XC7V2000T原理图元件库问题 | 09120313 | 1304/0 | 2015-07-17 23:32:59 by 09120313 |
| xps14.4建立K705的demo工程导入到edk14.4内，新建BSP，找不到LWIP的demo工程，为什么？ | lilianhu | 5610/1 | 2015-07-17 23:31:50 by 09120313 |
| Zynq 7020 JTAG 下载电路无法被IMpack 识别 | lilianhu | 1569/1 | 2015-07-17 23:29:55 by 09120313 |
| SelectIO Interface Wizard IP核是否支持subLVDS电平标准 | zhizihua209 | 2051/1 | 2015-07-17 22:52:19 by lilianhu |
| 这儿人多，再发一遍：逻辑和microblaze如何共同使用一片ddr3？ | himalaya0604 | 1621/1 | 2015-07-16 23:33:20 by muzhen2000 |
| 神马情况，输入信号怎么会被弄到IODELAY模块里过了一圈呢？ | 09120754 | 1516/1 | 2015-07-16 23:32:55 by muzhen2000 |
| 關於MicroBlaze+DDR3介面的設計 | himalaya0604 | 1184/0 | 2015-07-16 23:23:20 by himalaya0604 |
| 关于构建延迟线的请教 | himalaya0604 | 1714/0 | 2015-07-16 23:09:14 by himalaya0604 |
| iodelay的tap延迟问题 | 091217272 | 1580/1 | 2015-07-16 22:41:33 by himalaya0604 |
| 由IOB = true失败引发的问题 | 091217272 | 1071/0 | 2015-07-16 22:40:16 by 091217272 |
| ISE布局布线失败问题，求高手指教 | jjjjjjjjkkk | 1352/0 | 2015-07-15 23:39:55 by jjjjjjjjkkk |
| 关于FPGA的配置文件格式问题 | 09120581 | 1256/1 | 2015-07-15 23:13:19 by jjjjjjjjkkk |
| 请教如何正确给FPGA的输入时钟和输出时钟分配引脚 | caonimab | 1683/1 | 2015-07-15 23:11:51 by 09120581 |
| vivado能识别ise综合生成的网表文件.ngc的吗？ | zxzzy2009 | 1893/0 | 2015-07-15 22:50:33 by zxzzy2009 |
| 基于Xilinx Zynq的物距测量系统设计与实现 | zxzzy2009 | 1685/0 | 2015-07-15 22:34:46 by zxzzy2009 |
| ADAS和通向无人驾驶汽车之路 | zxzzy2009 | 1278/0 | 2015-07-15 22:17:53 by zxzzy2009 |
| 7系列iodelay与Virtex-5的iodelay结构 | himalaya0604 | 1455/1 | 2015-07-14 22:58:05 by czh306 |
| zynq从SD卡启动Linux失败 | himalaya0604 | 1692/1 | 2015-07-14 22:57:46 by czh306 |
| Virtex-6（ML605）板子配置千兆以太网，请指教！ | himalaya0604 | 1430/1 | 2015-07-14 22:57:11 by czh306 |
| 使用ac97实现音频回环问题 | himalaya0604 | 1355/0 | 2015-07-14 22:17:23 by himalaya0604 |
| 如何通过ethernet连接两块或多块fpga数据传输 | himalaya0604 | 1278/0 | 2015-07-14 22:15:52 by himalaya0604 |
| SDK PS initialization failed | toeflsieasy | 2212/1 | 2015-07-13 23:15:07 by toeflsieasy |
| zc702 devicetree問題 | jjjjjjjjkkk | 1375/1 | 2015-07-13 23:14:50 by toeflsieasy |
| 高速ADC 数据接收 | jjjjjjjjkkk | 1317/1 | 2015-07-13 23:14:30 by toeflsieasy |
| 关于z7与cameralink full的对接 | jjjjjjjjkkk | 1588/1 | 2015-07-13 23:14:17 by toeflsieasy |
| 用MIG为A7 XC7A75T fpga 生成ddr3 IP核的问题 | jjjjjjjjkkk | 1535/1 | 2015-07-13 23:13:23 by toeflsieasy |
| V6和K7的RAPID IO传数问题 | jjjjjjjjkkk | 1536/0 | 2015-07-13 22:33:27 by jjjjjjjjkkk |
| 关于xlinx sprtan-6 系列FPGA XC6SLX9-2TQG144C 时钟和 PLL 问题 | lilianhu | 5939/0 | 2015-07-12 22:54:32 by lilianhu |
| xc95144xl -5tq100复位信号问题 | lilianhu | 7222/0 | 2015-07-12 22:51:19 by lilianhu |
| Question about Kintex-7 HR bank LVDS bus | lilianhu | 1599/0 | 2015-07-12 22:36:07 by lilianhu |
| Virtex 7 VC709 与 Spantan6 Aurora 连接问题 | lilianhu | 1489/0 | 2015-07-12 22:35:13 by lilianhu |
| 如何使CPLD引脚输出高阻状态 | lilianhu | 1270/0 | 2015-07-12 22:13:38 by lilianhu |
| 用Tcl定制Vivado设计实现流程 | xilinx论坛 | 1586/0 | 2015-07-11 23:06:46 by xilinx论坛 |