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我的设计中采用K7 系列325T进行设计，设计中高速LVDS数据线使用了很多，被迫采用HR bank的管脚作为接收，大概需要五六十对LVDS差分线，根据设计手册中给出的HR bank 双沿数据率可以达到1250Mbps(设计中需要约为1000Mbps),通过官方提供的IBIS模型进行仿真分析，发现反射非常明显，数据发送端眼图质量非常差（FPGA为数据接收端）。初步分析原因是因为IBIS中FPGA HR bank中IN-TERM典型值为77欧姆。而LVDS采用100欧姆差分线，端接期望值为100欧姆有较大偏差导致。那么该手册中说明的1250Mbps速率是在什么情况下实现的？是否是在通过外部准确的100欧姆端接电阻实现的？那么在我的设计中是否要将FPGA中LVDS接收管脚差分对，都添加外部的100欧姆端接电阻才能达到1250Mbps的数据率？

Thank you for your attention!
I did a design the FPGA of K7 series 325T-2.The design with Dozens of high-speed LVDS lines .
According to the design manual is given in HR bank double along the data rate can reach 1250Mbps (design need about 1000 Mbps), provided by the official of the IBIS model simulation analysis, it is found that reflection is very obvious, the data transmitting eye quality verybad (FPGA as the data receiving end). The reason for the initial analysis is because the IBIS of the HR bank IN-TERM in FPGA is typically 77 ohm. LVDS uses 100 ohm differential line terminal, expected value is 100 ohms to have large deviation. Then what is the 1250Mbps rate achieved in the manual? Is the implementation of a 100 ohm termination resistor in an external accuracy? So in my design whether to LVDS FPGA receiver pin difference, both add external 100 ohm termination resistor to achieve the 1250Mbps data rate?