Xilinx|
版主: 51FPGA Q & A |
Xilinx
标题  |
作者 | 查看/回复 | 最后发表 |
|---|---|---|---|
| Virtex-5 fpga音频/视频连接解决方案 | Rancho | 1131/0 | 2012-06-19 09:35:23 by Rancho |
| 新代扩频时钟Spartan-6FPGAs | Rancho | 1179/0 | 2012-06-19 09:32:15 by Rancho |
| Spartan-3E/ 3 fpga 1:7反序列化速度高达666 Mbps | Rancho | 1244/0 | 2012-06-19 09:29:40 by Rancho |
| 参考设计:Logicore OPB USB 2.0设备 | Rancho | 1087/0 | 2012-06-19 09:27:36 by Rancho |
| 在Spartan3E/ 3 fpga7:1序列化中速度高达666 Mbps | Rancho | 1119/0 | 2012-06-19 09:26:08 by Rancho |
| 使用现有的电缆建立下一代宽带网络基础设施 | Rancho | 1017/0 | 2012-06-19 09:20:53 by Rancho |
| 利用CoolRunner-II CPLD设计数码相机 | Rancho | 1044/0 | 2012-06-19 09:17:18 by Rancho |
| 色彩空间转换器：YCrCb - RGB | Rancho | 1043/0 | 2012-06-19 09:15:46 by Rancho |
| Chroma Resampler | Rancho | 998/0 | 2012-06-19 09:14:33 by Rancho |
| 二维列序滤波器 (Rank Order Filter) | Rancho | 1295/0 | 2012-06-19 09:10:40 by Rancho |
| Xilinx软件安装事项 | jhp79 | 1674/2 | 2012-06-17 07:49:15 by dong130300 |
| ucf文件的编写 | baijunyan | 3048/4 | 2012-06-14 15:19:47 by l0p0c |
| ISE 的License问题 | baijunyan | 2560/3 | 2012-06-11 08:27:11 by baijunyan |
| FPGA助力中国智造，拥抱嵌入式计算新时代 | jackwang | 1530/2 | 2012-06-09 18:34:16 by bobgeng |
| Chroma Resampler | Rancho | 995/0 | 2012-06-02 15:22:32 by Rancho |
| 高密度算术函数实现的设计技巧 | Rancho | 1156/0 | 2012-06-02 15:14:35 by Rancho |
| 实现并转串，调试结果不对，找不到问题，请教大家 | minisnowy | 1973/3 | 2012-05-31 11:48:57 by 芯创电子工作室 |
| FPGA编译ModelSim需要的Xilinx库 | jhp79 | 1562/1 | 2012-05-25 12:26:49 by h254479169 |
| 参考系统：决定 DDR 反馈时钟的最佳 DCM 相移 | Rancho | 1379/1 | 2012-05-25 12:26:20 by h254479169 |
| 用 Xilinx CPLD 与 NAND Flash 存储器器件接口 | Rancho | 1548/1 | 2012-05-25 12:25:45 by h254479169 |
| FIR Compiler IP Core问题求助 | wwmumu | 7420/18 | 2012-05-20 11:13:33 by pengyanyun |
| FPGA实现高清信号的实时解码 | winthony | 1356/0 | 2012-05-17 16:15:23 by winthony |
| 为什么Xilinx器件中BRAM大小是18K？ | jhp79 | 1535/0 | 2012-05-16 12:18:45 by jhp79 |
| 小调查：你对下面哪些FPGA器件感兴趣？ | lemonsky | 1595/5 | 2012-05-16 08:59:24 by xtqxtq1111 |
| Vivado 赛灵思最新设计开发套件 | winthony | 1328/0 | 2012-05-15 11:35:20 by winthony |
| 高效的移位寄存器、LFSR 计数器和长伪随机序列发生器 | Rancho | 1434/0 | 2012-05-13 09:55:33 by Rancho |
| 将 DDR SDRAM 与 CoolRunner-II CPLD 接口 | Rancho | 1280/0 | 2012-05-13 09:52:30 by Rancho |
| 利用 CoolRunner-II CPLD 和 SPI 闪存配置 Xilinx FPGA | Rancho | 1386/0 | 2012-05-13 09:51:39 by Rancho |
| 无需板仿真即可估计实际的输出时序 | Rancho | 1229/0 | 2012-05-13 09:50:54 by Rancho |
| 133 MHz PCI-X 到128 MB DDR 小型 DIMM 存储器桥 | Rancho | 1179/0 | 2012-05-13 09:50:07 by Rancho |
| Virtex-5 系列高级封装 | Rancho | 1159/0 | 2012-05-13 09:49:20 by Rancho |
| 单纠错和双检错（中文版） | Rancho | 1263/0 | 2012-05-13 09:47:26 by Rancho |
| 利用 Virtex-4 器件实现 QDR II SRAM 接口（中文版） | Rancho | 1425/0 | 2012-05-13 09:46:27 by Rancho |
| 使用 Virtex-4 FPGA 器件实现 DDR SDRAM 控制器（中文版） | Rancho | 1447/0 | 2012-05-13 09:45:31 by Rancho |
| 利用 Xilinx FPGA 和存储器接口生成器简化存储器接口（中文版） | Rancho | 1264/0 | 2012-05-13 09:44:38 by Rancho |
| 将 64 位 DDR 存储器总线与 32 位微处理器总线接口 | Rancho | 1307/0 | 2012-05-13 09:43:31 by Rancho |
| 使用 ISERDES 和 OSERDES 实现高性能 DDR2 SDRAM 接口数据采集 | Rancho | 1696/0 | 2012-05-13 09:42:27 by Rancho |
| 利用直接时钟控制技术实现 DDR2 SDRAM 物理层 | Rancho | 1250/0 | 2012-05-13 09:41:31 by Rancho |
| 用于实现 RAID6 奇偶性的硬件加速器 | Rancho | 1234/0 | 2012-05-13 09:40:44 by Rancho |
| 存储器接口应用指南概述 | Rancho | 1161/0 | 2012-05-13 09:39:50 by Rancho |