XAPP1205片段：
ZC702_I2C_CONFIG zc702_hdmi_config[ZC702_HDMI_CONFIG_LEN] =
{
{0x41, 0x00, 0x10}, // Power Down Control
// R0x41[ 6] = PowerDown = 0 (power-up)
{0xD6, 0x00, 0xC0}, // HPD Control
// R0xD6[7:6] = HPD Control = 11 (always high)
{0x15, 0x00, 0x01}, // Input YCbCr 4:2:2 with separate syncs
{0x16, 0x00, 0x38}, // Output format 444, Input Color Depth = 8
// R0x16[ 7] = Output Video Format = 0 (444)
// R0x16[5:4] = Input Video Color Depth = 11 (8 bits/color)
// R0x16[3:2] = Input Video Style = 10 (style 1)
// R0x16[ 1] = DDR Input Edge = 0 (falling edge)
// R0x16[ 0] = Output Color Space = 0 (RGB)
{0x18, 0x00, 0xE7}, // Color Space Conversion
// R0x18[ 7] = CSC enable = 1 (CSC enabled)
// R0x18[6:5] = CSC Scaling Factor = 11 (+/- 4.0, -16384 - 16380)
// R0x18[4:0] = CSC coefficient A1[12:8] = 00111
{0x19, 0x00, 0x34}, // R0x19[7:0] = CSC coefficient A1[ 7:0] = 00110100
{0x1A, 0x00, 0x04}, // R0x1A[ 5] = CSC coefficient update
// R0x1A[4:0] = CSC coefficient A2[12:8] = 00100
{0x1B, 0x00, 0xAD}, // R0x1B[7:0] = CSC coefficient A2[ 7:0] = 10101101
{0x1C, 0x00, 0x00}, // R0x1C[4:0] = CSC coefficient A3[12:8] = 00000
{0x1D, 0x00, 0x00}, // R0x1D[7:0] = CSC coefficient A3[ 7:0] = 00000000
{0x1E, 0x00, 0x1C}, // R0x1E[4:0] = CSC coefficient A4[12:8] = 11100
{0x1F, 0x00, 0x1B}, // R0x1F[7:0] = CSC coefficient A4[ 7:0] = 00011011
{0x20, 0x00, 0x1D}, // R0x20[4:0] = CSC coefficient B1[12:8] = 11101
{0x21, 0x00, 0xDC}, // R0x21[7:0] = CSC coefficient B1[ 7:0] = 11011100
{0x22, 0x00, 0x04}, // R0x22[4:0] = CSC coefficient B2[12:8] = 00100
{0x23, 0x00, 0xAD}, // R0x23[7:0] = CSC coefficient B2[ 7:0] = 10101101
{0x24, 0x00, 0x1F}, // R0x24[4:0] = CSC coefficient B3[12:8] = 11111
{0x25, 0x00, 0x24}, // R0x25[7:0] = CSC coefficient B3[ 7:0] = 00100100
{0x26, 0x00, 0x01}, // R0x26[4:0] = CSC coefficient B4[12:8] = 00001
{0x27, 0x00, 0x35}, // R0x27[7:0] = CSC coefficient B4[ 7:0] = 00110101
{0x28, 0x00, 0x00}, // R0x28[4:0] = CSC coefficient C1[12:8] = 00000
{0x29, 0x00, 0x00}, // R0x29[7:0] = CSC coefficient C1[ 7:0] = 00000000
{0x2A, 0x00, 0x04}, // R0x2A[4:0] = CSC coefficient C2[12:8] = 00100
{0x2B, 0x00, 0xAD}, // R0x2B[7:0] = CSC coefficient C2[ 7:0] = 10101101
{0x2C, 0x00, 0x08}, // R0x2C[4:0] = CSC coefficient C3[12:8] = 01000
{0x2D, 0x00, 0x7C}, // R0x2D[7:0] = CSC coefficient C3[ 7:0] = 01111100
{0x2E, 0x00, 0x1B}, // R0x2E[4:0] = CSC coefficient C4[12:8] = 11011
{0x2F, 0x00, 0x77}, // R0x2F[7:0] = CSC coefficient C4[ 7:0] = 01110111
{0x48, 0x00, 0x08}, // Video Input Justification
// R0x48[8:7] = Video Input Justification = 01 (right justified)
{0x55, 0x00, 0x00}, // Set RGB in AVinfo Frame
// R0x55[6:5] = Output Format = 00 (RGB)
{0x56, 0x00, 0x28}, // Aspect Ratio
// R0x56[5:4] = Picture Aspect Ratio = 10 (16:9)
// R0x56[3:0] = Active Format Aspect Ratio = 1000 (Same as Aspect Ratio)
{0x98, 0x00, 0x03}, // ADI Recommended Write
{0x9A, 0x00, 0xE0}, // ADI Recommended Write
{0x9C, 0x00, 0x30}, // PLL Filter R1 Value
{0x9D, 0x00, 0x61}, // Set clock divide
{0xA2, 0x00, 0xA4}, // ADI Recommended Write
{0xA3, 0x00, 0xA4}, // ADI Recommended Write
{0xAF, 0x00, 0x04}, // HDMI/DVI Modes
// R0xAF[ 7] = HDCP Enable = 0 (HDCP disabled)
// R0xAF[ 4] = Frame Encryption = 0 (Current frame NOT HDCP encrypted)
// R0xAF[3:2] = 01 (fixed)
// R0xAF[ 1] = HDMI/DVI Mode Select = 0 (DVI Mode)
{0xE0, 0x00, 0xD0}, // Must be set to 0xD0 for proper operation
{0xF9, 0x00, 0x00} // Fixed I2C Address (This should be set to a non-conflicting I2C address)
};
Xilinx
