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版主: 51FPGA |
关于在ISE14.4中调用modelsim6.5进行功能仿真的问题
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SCOFEEL
最后登陆时间：2015-01-13 22:10:09 |
modelsim6.5在打开运行时出现下面错误，无法继续进行，求大侠指教一二，谢谢！ Top level modules:# glbl # vsim -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -lib work -voptargs=\"+acc\" -t 1ps work.top_tb glbl # ** Note: (vsim-3812) Design is being optimized... # ** Error: DCM0.v(95): Module 'DCM_SP' is not defined. # ** Error: DCM0.v(120): Module 'DCM_SP' is not defined. # ** Error: DCM0.v(122): Module 'BUFG' is not defined. # ** Error: DCM0.v(124): Module 'IBUFG' is not defined. # ** Error: DCM0.v(126): Module 'BUFG' is not defined. # ** Error: DCM0.v(128): Module 'INV' is not defined. # ** Error: DCM0.v(130): Module 'BUFG' is not defined. # ** Error: DCM0.v(132): Module 'BUFG' is not defined. # ** Error: DCM0.v(134): Module 'BUFG' is not defined. # ** Error: DCM0.v(138): Module 'FDS' is not defined. # ** Error: DCM0.v(141): Module 'FD' is not defined. # ** Error: DCM0.v(144): Module 'FD' is not defined. # ** Error: DCM0.v(147): Module 'FD' is not defined. # ** Error: DCM0.v(150): Module 'OR2' is not defined. # ** Error: DCM0.v(154): Module 'OR3' is not defined. # ** Error: tx_fifo0.v(182): Module 'FIFO_GENERATOR_V4_4' is not defined. # Optimization failed # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./top_tb.fdo PAUSED at line 33 |
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