版主: 51FPGA

分享到:
共1条 1/1 1   

Using System Generator for Systematic HDL Deisng, Verification, and Validation

    [您是本帖的第1159位阅读者]
Rancho
我是GG
高级会员

最后登陆时间:2015-01-14 09:17:39

直达楼层
1# 发表于 2012-05-13 08:51:02

Using SystemGenerator, users can functionally simulate a design and use the MATLAB® environment to verify the bit/cycle-tru model against the golden reference results, produced either externally or inside the MATLAB environemnt.

wp283.pdf




关键词:Using    System    Generator    Sy    

Rancho。

共1条 1/1 1   
快速回复主题
  • 匿名不能发帖!请先 [ 登陆 注册 ]