Connecting Virtex-6 FPGAs to ADCs with Serial LVDS Interfaces and DACs with Para

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Connecting Virtex-6 FPGAs to ADCs with Serial LVDS Interfaces and DACs with Para

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1^# 发表于 2012-05-09 18:57:03

This application note describes how to utilize the dedicated deserializer(ISERDES) and serializer (OSERDES) functionalities in Virtex®-6 FPGAs to interface with analog-to-digital converters that have serial low-voltage differential signaling (LVDS) outputs and with digital-to-analog converters that have parallel LVDS inputs.

xapp1071_V6_ADC_DAC_LVDS.pdf

关键词：Connecting Virtex-6 FPGAs

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