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10 Gigabit Ethernet/Fibre Channel PCS Reference Design - Not Recommended for New

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1# 发表于 2012-05-09 18:32:39

This application note describes the 10 Gigabit Ethernet Physical Coding Sublayer (PCS) reference design for Xilinx Virtex™-II and Virtex-II Pro FPGAs. The PCS connects between a Xilinx RocketPHY™ 10 Gb/s transceiver and the Xilinx LogiCORE™ 10 Gigabit Ethernet Media Access Controller (MAC) core, LogiCORE XAUI core or 10 Gigabit Media Independent Interface (XGMII) Reference Design (XAPP606). This product is not recommended for new designs.

xapp775.pdf




关键词:Gigabit    Ethernet    Fibre    Ch    

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