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综合告警信息 -- WARNING:Xst:3002

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ponyhk
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最后登陆时间:2018-08-17 20:18:49

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1# 发表于 2019-04-06 16:18:57
WARNING:Xst:3002 - This design contains one or more registers/latches that are directly
   incompatible with the Spartan6 architecture. The two primary causes of this is
   either a register or latch described with both an asynchronous set and
   asynchronous reset, or a register or latch described with an asynchronous
   set or reset which however has an initialization value of the opposite 
   polarity (i.e. asynchronous reset with an initialization value of 1).

While this circuit can be built, it creates a sub-optimal implementation

in terms of area, power and performance. For a more optimal implementation

Xilinx highly recommends one of the following:


1) Remove either the set or reset from all registers and latches

if not needed for required functionality

2) Modify the code in order to produce a synchronous set

and/or reset (both is preferred)

3) Ensure all registers have the same initialization value as the

described asynchronous set or reset polarity

4) Use the -async_to_sync option to transform the asynchronous

set/reset to synchronous operation

(timing simulation highly recommended when using this option)

没有提示是代码什么地方,请问如何解决?




关键词:WARNING:Xst:3002    

RE: 综合告警信息 -- WARNING:Xst:3002

ponyhk
性别保密
普通会员

最后登陆时间:2018-08-17 20:18:49

2# 发表于 2019-04-06 16:34:54
ponyhk的原帖
WARNING:Xst:3002 - This design contains one or more registers/latches that are directly
   incompatible with the Spartan6 architecture. The two primary causes of this is
   either a register or latch described with both an asynchronous set and
   asynchronous reset, or a register or latch described with an asynchronous
   set or reset which however has an initialization value of the opposite 
   polarity (i.e. asynchronous reset with an initialization value of 1).

While this circuit can be built, it creates a sub-optimal implementation

in terms of area, power and performance. For a more optimal implementation

Xilinx highly recommends one of the following:


1) Remove either the set or reset from all registers and latches

if not needed for required functionality

2) Modify the code in order to produce a synchronous set

and/or reset (both is preferred)

3) Ensure all registers have the same initialization value as the

described asynchronous set or reset polarity

4) Use the -async_to_sync option to transform the asynchronous

set/reset to synchronous operation

(timing simulation highly recommended when using this option)

没有提示是代码什么地方,请问如何解决?


问题解决。

告警原因是:

1、寄存器或信号量(总之需要锁存的)有个初始值;

2、在复位电路汇中,又赋予了和定义时候不同的值;

就会导致告警。

比如:

signal power_on    : std_logic := '0';


if (RST_IN = '0') then

    power_on  <= '1';            -- 告警

else

end if;

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