出现这个错误Warning:Xst:37 - Detected unknow constraint/property "NOPRUNE". This constraint/property is not supported by the currented by the current software release and will be ignored

怎么解决？

下面是程序

module uart_rx_top(
clk50m,
rst_n,
rxd,
rx_data,
rx_over
    );
input clk50m;
input rst_n;
input rxd;
output [7:0]rx_data;
output rx_over;

wire intt;
wire clk_bps;

uart_spd     speed_rx(
                      .clk50m(clk50m),
                      .rst_n(rst_n),
                      .intt(intt),
                      .clk_bps(clk_bps)
                     );
                     
uart_rx      uart_rx(
                      .clk50m(clk50m),
                     .rst_n(rst_n),
                     .clk_bps(clk_bps),                      
                      .rxd(rxd),
                      .rx_data(rx_data),
                      .bps_start(intt),
                      .rx_over(rx_over)
                      );
endmodule


module uart_rx 
   (
       clk50m,
        clk_bps,
       rst_n,
       rxd,
       rx_data,
       bps_start,
        rx_over
  )/*synthesis noprune*/;
  
  input clk50m;
  input rst_n;
  input rxd; //RS232接收数据信号
  input clk_bps; //波特率的16倍
  output wire bps_start; //波特率时钟启动信号置位，应该为一个大于1T（50MHz）的脉冲
  output reg[7:0] rx_data; //接收数据寄存器，保存直至下一个数据到来
  output reg rx_over; //接收数据完成

reg [3:0] cnt; //
reg [3:0] scnt;//周期计数，波特率发生器的输出时钟为实际串口数据波特率的N倍，N=16
reg [7:0] rx_data_reg;

reg [2:0]state,next_state; //当前状态和下一个状态
reg RN0,RN1,RN2,RN3,RN4,RN5,RN6; //控制寄存器
parameter SN0=3'd0, SN1=3'd1, //状态
      SN2=3'd2, SN3=3'd3,  
          SN4=3'd4, SN5=3'd5,SN6=3'd6;
parameter NUM     =4'd15; //sclk脉冲个数16个
parameter half_NUM=4'd7;
parameter SNUM    =3'd7; //

//-------------状态转换---------------//
always @ (posedge clk_bps or negedge rst_n)begin
    if(!rst_n)
        state <= SN0;
    else
        state <= next_state;
end
//----------时序逻辑----------//
always @ (state,rst_n,cnt,scnt,rx_over,rx_data_reg,rxd) begin
RN0<= 1'b0; RN1<= 1'b0; RN2<= 1'b0; RN3<= 1'b0;
RN4<= 1'b0; RN5<= 1'b0; RN6<= 1'b0; 
case(state)
SN0:begin             //0
    RN0      <= 1'b1;
    if(!rst_n)
        next_state <= SN0;
    else if(rxd)
        next_state <= SN0;
    else 
        next_state <= SN1;
    end 
SN1:begin //1
    RN1   <= 1'b1;
    if(cnt>=3'd6)
        next_state <= SN2;
    else
        next_state <= SN1;
    end
SN2:begin //2,检查第一位数据的中间时段是否为0
    RN2   <= 1'b1;
    if(!rxd)
        next_state <= SN3;
    else
        next_state <= SN0;
    end
SN3:begin //3
    RN3   <= 1'b1;
    if(cnt>=NUM-1'd1)
        next_state <= SN4;
    else
        next_state <= SN3;
    end
SN4:begin //4
    RN4 <=1'b1;
    if(scnt>=SNUM)
        next_state <= SN5;
    else
        next_state <= SN3;
    end
SN5:begin
    RN5 <=1'b1;
    if(cnt>=NUM)
        next_state <= SN6;
    else
        next_state <= SN5;
    end
SN6:begin
    RN6 <=1'b1;
    next_state <= SN0;
    end
  default: next_state <= SN0;
endcase
end
//--------寄存器数据操作--------//
always @ (posedge clk_bps) begin
if(RN0)
    begin
        cnt <= 4'd0;
        scnt <= 4'd0;
        rx_data_reg <= 8'd0;
         rx_over <= 1'd0;
    end
    else if(RN1)
    begin
         cnt <= cnt+1'd1;
        scnt <= 4'd0;
        rx_data_reg <= 8'd0;
         rx_over <= 1'd0;
    end
else if(RN2)
    begin
        cnt <= 4'd0;
        scnt <= 4'd0;
        rx_data_reg <= 8'd0;
         rx_over <= 1'd0;
    end
else if(RN3)
    begin
        cnt <= cnt+1'd1;
        rx_over <= 1'd0;
    end
else if(RN4)
    begin
        cnt <= 4'd0;
        scnt <= scnt+1'd1;
        rx_data_reg[7-scnt]<= rxd;
         rx_over <= 1'd0;
    end
else if(RN5)
    begin
        cnt <= cnt+1'd1;
        scnt <= 4'd0;
        rx_over <= 1'd0;
    end
else if(RN6)
    begin
        cnt <= 4'd0;
        scnt <= 4'd0;
        rx_over <= 1'd1;
    end
else
    begin
        cnt <= 4'd0;
        scnt <= 4'd0;
        rx_data_reg <= 8'd0;
        rx_over <= 1'd0;
    end
end

reg [2:0]bps;
always @ (posedge clk50m or negedge rst_n) begin
if(!rst_n)
          bps <= 3'd0;
else 
    begin
          bps[2] <= bps[1];
          bps[1] <= bps[0];
          bps[0] <= rxd;
    end
end
////检测当state=0时，aa=1，只在状态0时，才会给波特率模块发中断

reg aa;
always @ (posedge clk50m) begin
if(state==0)
    aa <=1'd1;
else
    aa <=1'd0;
end
assign bps_start=(~bps[0])&bps[2]&bps[1]&aa;

/////////////将数据打到外部端口////////////////////
reg bb;
always @ (posedge clk50m) begin ////增加rx_over的驱动能力，减小rx_over的倾斜
if(rx_over==1'b1) bb <=1'd1;
else       bb <=1'd0;
end
always @ (posedge bb or negedge rst_n)begin
if(!rst_n)
    rx_data <= 8'd0;
else
    rx_data <= rx_data_reg;
end


endmodule


module uart_spd(
   clk50m,
rst_n,
intt,
clk_bps
);
input clk50m;     //50MHZ
input rst_n;       //the low level is valid
input intt; //宽度大于1个T（50MHz）的高电平即可
output reg clk_bps; //分频输出信号，，，//9600*32=307.2kb/s----//50m/307.2k=162
 
parameter BPS_PARA   = 162-2;  //162--9600//81--19200
parameter haf_BPS = (BPS_PARA/2)-1;


reg [7:0] cnt; //
reg [2:0]state,next_state; //当前状态和下一个状态
reg RN0,RN1,RN2,RN3; //控制寄存器
parameter SN0=3'd0, SN1=3'd1, //状态
      SN2=3'd2, SN3=3'd3;


always @(posedge clk50m or negedge rst_n)begin
if(!rst_n)
state <= SN0;
else if(intt)
state <= SN0;
else 
state <= next_state;
end


always @ (state,rst_n,intt,cnt,clk_bps)
begin
RN0<= 1'b0; RN1<= 1'b0; RN2<= 1'b0; RN3<= 1'b0;
case(state)
SN0:begin             //0
RN0      <= 1'b1;
if(intt)
next_state <= SN0;
else if(!rst_n)
next_state <= SN0;
else
next_state <= SN1;
end
SN1:begin //1
RN1   <= 1'b1;
if(cnt>=haf_BPS)
next_state <= SN2;
else
next_state <= SN1;
end
SN2:begin //2
RN2   <= 1'b1;
if(cnt>=BPS_PARA)
next_state <= SN3;
else
next_state <= SN2;
end
SN3:begin //3
RN3   <= 1'b1;
next_state <= SN0;
end
  default: next_state <= SN0;
endcase
end


//--------寄存器数据操作--------//
always @ (posedge clk50m)
begin
if(RN0)
begin
cnt <= 8'd0;
clk_bps <= 1'b0;
end
    else if(RN1) begin
cnt <= cnt+1'b1;
clk_bps <= 1'b0;
end
else if(RN2)
begin
cnt <= cnt+1'b1;
clk_bps <= 1'b1;
end
else if(RN3)
begin
cnt <= 8'd0;
clk_bps <= 1'b1;
end
else begin
cnt <= 8'd0;
clk_bps <= 1'b0;
end
end

endmodule