大家好~

看别人的工程可以生成下面的ucf。不知道该怎么弄。求大神赐教~

就是通过MPMC控制DDR2时序

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# Define multicycle paths - these paths may take longer because additional
# time allowed for logic to settle in calibration/initialization FSM
###############################################################################


# MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
#          multicycle paths from originating flip-flop to ANY destination
#          flip-flop (or in some cases, it can also be a BRAM)
# MUX Select for either rising/falling CLK0 for 2nd stage read capture
INST "*/mpmc_0/*/u_phy_calib_0/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL_C0";
TIMESPEC TS_MC_RD_DATA_SEL_C0 = FROM "TNM_RD_DATA_SEL_C0" TO  FFS 40 ns;
# MUX select for read data - optional delay on data to account for byte skews
#INST "mpmc_0/*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX_C0";
#TIMESPEC "TS_MC_RDEN_SEL_MUX_C0" = FROM "TNM_RDEN_SEL_MUX_C0" TO FFS
#"TS_SYS_CLK" * 4;
# Calibration/Initialization complete status flag (for PHY logic only) - can
# be used to drive both flip-flops and BRAMs
INST "*/mpmc_0/*/u_phy_init_0/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL_C0";
TIMESPEC TS_MC_PHY_INIT_DATA_SEL_0_C0 = FROM "TNM_PHY_INIT_DATA_SEL_C0" TO  FFS 40 ns;
TIMESPEC TS_MC_PHY_INIT_DATA_SEL_90_C0 = FROM "TNM_PHY_INIT_DATA_SEL_C0" TO  RAMS 40 ns;
# Select (address) bits for SRL32 shift registers used in stage3/stage4
# calibration
INST "*/mpmc_0/*/u_phy_calib_0/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY_C0";
TIMESPEC TS_MC_GATE_DLY_C0 = FROM "TNM_GATE_DLY_C0" TO  FFS 40 ns;
INST "*/mpmc_0/*/u_phy_calib_0/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY_C0";
TIMESPEC TS_MC_RDEN_DLY_C0 = FROM "TNM_RDEN_DLY_C0" TO  FFS 40 ns;
INST "*/mpmc_0/*/u_phy_calib_0/gen_cal_rden_dly*.u_ff_cal_rden_dly" TNM = "TNM_CAL_RDEN_DLY_C0";
TIMESPEC TS_MC_CAL_RDEN_DLY_C0 = FROM "TNM_CAL_RDEN_DLY_C0" TO  FFS 40 ns;