if((temp&(state==2'b10)&(sp[15:0]==8'hf0))or((state==2'b11)&(sp[15:0]==8'hf0)&temp)) begin
state<=2'b00;
cin<=0;
if(count_1==10)
con_1=8'h00;
count_1=0;
if(count_2==10)
con_2=8'h00;
count_2=0;
end
cin<=0;
end
///////////////////////////////////////////////////////////////
//状态选择程序：state00为寻找标签
//01为目的地址确定
//10为净荷汇聚到1端口，11为净荷汇聚到2端口
//////////////////////////////////////////////////////////
always@(posedge clk) begin
if(temp&state==2'b10)
con_1<=sp[7:0];
cin<=0;
if(temp&state==2'b11)
con_2<=sp[7:0];
cin<=0;
end
endmodule

ERROR:HDLCompiler:806 - "F:/ISEPROJECT/contrition/contrition.v" Line 60: Syntax error near "or".
ERROR:HDLCompiler:806 - "F:/ISEPROJECT/contrition/contrition.v" Line 77: Syntax error near "always".
ERROR:HDLCompiler:806 - "F:/ISEPROJECT/contrition/contrition.v" Line 85: Syntax error near "endmodule".
ERROR:ProjectMgmt - 3 error(s) found while parsing design hierarchy.