请教一个CPU与FPGA接口时序约束的问题，下图是CPU测接口时序：

现在的约束如下：
1. 对地址锁存信号，分别对信号上升沿和下降沿设置input delay
set_input_delay -rise -max -clock [get_clocks {CLK}]  t11max [get_ports {ALE}]
set_input_delay -rise -min -clock [get_clocks {CLK}]  t11min [get_ports {ALE}]
set_input_delay -add_delay -fall -max -clock [get_clocks {CLK}]  t21max [get_ports {ALE}] 
set_input_delay -add_delay -fall -min -clock [get_clocks {CLK}]  t21min [get_ports {ALE}] 
2. 对片选信号：
set_input_delay -rise -max -clock [get_clocks {CLK}]  t24max [get_ports {CPU_CS1 CPU_CS2}]
set_input_delay -rise -min -clock [get_clocks {CLK}]  t24min [get_ports {CPU_CS1 CPU_CS2}]
set_input_delay -add_delay -fall -max -clock [get_clocks {CLK}]  t14max [get_ports {CPU_CS1 CPU_CS2}] 
set_input_delay -add_delay -fall -min -clock [get_clocks {CLK}]  t14min [get_ports {CPU_CS1 CPU_CS2}] 

3. 对读信号和写信号约束：
set_input_delay -rise -max -clock [get_clocks {CLK}]  t20x [get_ports {CPU_WRH CPU_WRL}]
set_input_delay -rise -min -clock [get_clocks {CLK}]  t20n [get_ports {CPU_WRH CPU_WRL}]
set_input_delay -add_delay -fall -max -clock [get_clocks {CLK}]  t10max [get_ports {CPU_WRH CPU_WRL}] 
set_input_delay -add_delay -fall -min -clock [get_clocks {CLK}]  t10min [get_ports {CPU_WRH CPU_WRL}] 
4. FPGA-TO-CPU的数据输出
set_output_delay -clock {get_clocks {CLK}} -max t30 [get_ports {CPU_D}] -add_delay
set_output_delay -clock {get_clocks {CLK}} -min t31 [get_ports {CPU_D}] -add_delay
以上约束不知正确与否？
剩下还需要约束CPU-TO-FPGA的数据输入，不知该如何处理？