管脚约束配置完之后出现如下错误：
ERRORlace:1115 - Unroutable Placement! A clock IOB / BUFIO clock component pair have been found that are not placed at
   a routable clock IOB / BUFIO site pair. The clock IOB component <clkin> is placed at site <AD156>. The BUFIO
   component <SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0> is placed at site <BUFIO2_X0Y22>. Each BUFIO site has a select set of
   IOBs that can drive it. If these IOBs are not used, the connection is not routable You may want to analyze why this
   problem exists and correct it. This placement is UNROUTABLE in PAR and therefore, this error condition should be
   fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in FPGA Editor to debug the problem. A list
   of all the COMP.PINS used in this clock placement rule is listed below. These examples can be used directly in the
   .ucf file to demote this ERROR to a WARNING.
   < NET "clkin" CLOCK_DEDICATED_ROUTE = FALSE; >

主要问题出在clkin信号上，但如果我把下面这段删除，又没问题了
OBUFDS lvds_dataa_obuf0(.I(DATA_OUT[0]),  .O(dataouta_p[0]), .OB(dataouta_n[0]) );
OBUFDS lvds_dataa_obuf1(.I(DATA_OUT[1]),  .O(dataouta_p[1]), .OB(dataouta_n[1]) );
OBUFDS lvds_dataa_obuf2(.I(DATA_OUT[2]),  .O(dataouta_p[2]), .OB(dataouta_n[2]) );
OBUFDS lvds_dataa_obuf3(.I(DATA_OUT[3]),  .O(dataouta_p[3]), .OB(dataouta_n[3]) );
OBUFDS lvds_dataa_obuf4(.I(DATA_OUT[4]),  .O(dataouta_p[4]), .OB(dataouta_n[4]) );
OBUFDS lvds_dataa_obuf5(.I(DATA_OUT[5]),  .O(dataouta_p[5]), .OB(dataouta_n[5]) );
OBUFDS lvds_dataa_obuf6(.I(DATA_OUT[6]),  .O(dataouta_p[6]), .OB(dataouta_n[6]) );
OBUFDS lvds_dataa_obuf7(.I(DATA_OUT[7]),  .O(dataouta_p[7]), .OB(dataouta_n[7]) );
OBUFDS lvds_dataa_obuf8(.I(CLK_OUT[0]),  .O(CLK_O_P), .OB(CLK_O_N) );
OBUFDS lvds_dataa_obuf9(.I(CLK_OUT[1]),  .O(CLK_E_P), .OB(CLK_E_N) );
觉得好奇怪，上面这段程序并未涉及clkin信号，为什么会改正错误呢