module Pal_serial(clk,rst,din,dout,databuff);

input clk,rst;
input[6:0] din;
output dout;
output databuff;
wire dout;
reg [6:0]dbuff;
reg [6:0] databuff;
integer ii;
always @(posedge clk)
 begin
  if(!rst)
   begin
        databuff=7'b000_0000;
        dbuff=din;
      end         
   else
  for (ii=1;ii<7;ii=ii+1)
 
  databuff=dbuff<<ii; 
 end

assign dout=databuff[6];

endmodule