Xilinx|
版主: 51FPGA Q & A |
Xilinx
标题  |
作者 | 查看/回复 | 最后发表 |
|---|---|---|---|
| 面向 Virtex-4 FPGA 的可综合 CIO DDR RLDRAM II 控制器 | Rancho | 1699/0 | 2012-05-13 09:38:59 by Rancho |
| 更宽的块存储器 | Rancho | 1712/0 | 2012-05-13 09:37:36 by Rancho |
| XAPP702 - 使用 Virtex-4 器件实现 DDR2 控制器 | Rancho | 1696/0 | 2012-05-13 09:36:50 by Rancho |
| 面向Virtex™-II Pro FPGA的DDR2 SDRAM存储器接口 | Rancho | 1440/0 | 2012-05-13 09:35:44 by Rancho |
| 用于 RAID6 奇偶生成/数据恢复控制器的硬件加速器 | Rancho | 1910/0 | 2012-05-13 09:34:57 by Rancho |
| Using Digitally Controlled Impedance: Signal Integrity vs Power Dissipation Cons | Rancho | 2414/0 | 2012-05-13 09:33:38 by Rancho |
| 参考设计：带有 OPB 中心 DMA 的 MCH OPB EMC | Rancho | 1677/0 | 2012-05-13 09:31:36 by Rancho |
| 参考系统：带有 OPB 中心 DMA 的 PLB DDR2 | Rancho | 1831/0 | 2012-05-13 09:30:42 by Rancho |
| 从配置 PROM 读取用户数据 | Rancho | 1712/0 | 2012-05-13 09:29:46 by Rancho |
| 在 Spartan-3A FPGA 内实现 DDR2-400 存储器接口 | Rancho | 2066/0 | 2012-05-13 09:28:54 by Rancho |
| 使用 Virtex-4 器件的 DDR2 控制器（267 MHz 及以上） | Rancho | 1631/0 | 2012-05-13 09:27:45 by Rancho |
| Virtex-5 FPGAs RLDRAM II 寄存器接口 | Rancho | 1837/0 | 2012-05-13 09:26:55 by Rancho |
| Accelerating System Designs Requiring High-Bandwidth Connectivity with Targeted | Rancho | 1790/0 | 2012-05-13 09:26:06 by Rancho |
| High-Performance DDR2 SDRAM Interface in Virtex-5 Devices | Rancho | 1812/0 | 2012-05-13 09:25:10 by Rancho |
| The purpose of this white paper is to describe how Spartan®-6 FPGAs address the | Rancho | 1679/0 | 2012-05-13 09:24:03 by Rancho |
| Virtex 器件中的多个 CAM 设计概述 | Rancho | 1782/0 | 2012-05-13 09:16:50 by Rancho |
| Parameterizable LocalLink FIFO - Not Recommended for New Designs | Rancho | 1776/0 | 2012-05-13 09:15:47 by Rancho |
| Self-Addressing FIFO | Rancho | 1865/0 | 2012-05-13 09:14:58 by Rancho |
| FIFOs Using Virtex-II Block RAM - Obsolete | Rancho | 1813/0 | 2012-05-13 09:14:11 by Rancho |
| FIFOs Using Virtex-II Shift Registers - Obsolete | Rancho | 1805/0 | 2012-05-13 09:13:25 by Rancho |
| Serial-to-Parallel Converter - Obsolete | Rancho | 1583/0 | 2012-05-13 09:12:36 by Rancho |
| 170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature - Obsolete | Rancho | 1733/0 | 2012-05-13 09:11:45 by Rancho |
| FIFO Generator v2.2 | Rancho | 1710/0 | 2012-05-13 09:10:50 by Rancho |
| 利用 EMIF 接口 Xilinx FPGA 和 TI DSP 平台 | Rancho | 1831/0 | 2012-05-13 09:02:40 by Rancho |
| 使用DSP48 DDR 技术的Alpha Blending 2数据流 | Rancho | 1645/0 | 2012-05-13 09:01:27 by Rancho |
| Forward Error Correction on ITU-G.709 Networks using Reed-Solomon Solutions | Rancho | 1534/0 | 2012-05-13 08:59:05 by Rancho |
| A 3/4/5/6X Oversampling Circuit for 200 Mb/s to 1000 Mb/s Serial Interfaces( | Rancho | 1651/0 | 2012-05-13 08:58:08 by Rancho |
| Viterbi Decoder Block Decoding - Trellis Termination and Tail Biting | Rancho | 1683/0 | 2012-05-13 08:57:05 by Rancho |
| 数字电视广播系统内的前向纠错 | Rancho | 1701/0 | 2012-05-13 08:56:08 by Rancho |
| 使用 Spartan-II 的 Reed-Solomon 解决方案 | Rancho | 1705/0 | 2012-05-13 08:55:12 by Rancho |
| Virtex-4 FX 器件中的浮点单元 (FPU) 与 PowerPC 处理器 | Rancho | 1782/0 | 2012-05-13 08:54:09 by Rancho |
| Designing Efficient Digital Up and Down Converters for Narrowband Systems | Rancho | 1815/0 | 2012-05-13 08:53:13 by Rancho |
| Decreasing Simulation Runtimes with System Generator for DSP Hardware Co-Simulat | Rancho | 1696/0 | 2012-05-13 08:51:53 by Rancho |
| Using System Generator for Systematic HDL Deisng, Verification, and Validation | Rancho | 1791/0 | 2012-05-13 08:51:02 by Rancho |
| M2C-加速器简化了基于模型的设计 | Rancho | 1676/0 | 2012-05-13 08:49:35 by Rancho |
| AccelDSP IP 浏览器 | Rancho | 1607/0 | 2012-05-13 08:48:52 by Rancho |
| 针对 DSP 使用 MATLAB 为系统生成器创建 IP | Rancho | 1746/0 | 2012-05-13 08:47:58 by Rancho |
| AccelDSP 综合工具支持 MATLAB 结构和功能 | Rancho | 1839/0 | 2012-05-13 08:47:03 by Rancho |
| rtex 器件中的多个 CAM 设计概述 | Rancho | 1733/0 | 2012-05-11 21:41:19 by Rancho |
| Parameterizable 8b/10b Decoder | Rancho | 1116/0 | 2012-05-11 21:40:23 by Rancho |