Xilinx|
版主: 51FPGA Q & A |
Xilinx
标题  |
作者 | 查看/回复 | 最后发表 |
|---|---|---|---|
| 【每月有奖问答-开奖公告】你知道Vivado 2014.3 中的更新了哪些信息吗？ | nakey | 1048/2 | 2015-04-28 18:19:01 by hehequan |
| 关于bootloader | 2007zoz | 877/0 | 2015-04-21 21:56:15 by 2007zoz |
| 时序的几个概念 | pengrui | 969/0 | 2015-04-21 21:53:11 by pengrui |
| 利用赛灵思开发工具克服FPGA I/O引脚分配挑战 | tuozi241 | 1074/0 | 2015-04-21 21:51:19 by tuozi241 |
| FPGA开发要注意的十大要点 | WOAIMAC | 931/0 | 2015-04-21 21:48:25 by WOAIMAC |
| FPGA学习的一些误区 | inrxkj | 1017/0 | 2015-04-21 21:47:15 by inrxkj |
| 编写具有100%可靠性代码的几个技巧 | WOAIMAC | 1037/0 | 2015-04-19 18:11:13 by WOAIMAC |
| Verilog设计经验点滴 | inrxkj | 974/0 | 2015-04-19 18:09:59 by inrxkj |
| FPGA加载时间的研究 | abgh668 | 1014/0 | 2015-04-19 18:08:05 by abgh668 |
| FPGA verilog的编程心得 | lj1209 | 913/0 | 2015-04-19 18:05:56 by lj1209 |
| 求助下载连接问题 【Q & A】 | 舒奕榕 | 1058/0 | 2015-04-19 16:49:25 by 舒奕榕 |
| Testbench代码设计技巧 | zhizihua209 | 1007/0 | 2015-04-19 12:26:35 by zhizihua209 |
| 数字信号处理IP的误差舍入 | zhizihua209 | 929/0 | 2015-04-19 12:23:07 by zhizihua209 |
| Xilinx Smarter 网络解决方案中文字幕视频大全 | sydfeng | 893/0 | 2015-04-19 12:21:47 by sydfeng |
| Xilinx SERDES调试方法 | sydfeng | 1163/0 | 2015-04-19 12:20:12 by sydfeng |
| 参考时钟对SERDES性能的影响 | sydfeng | 1077/0 | 2015-04-19 12:18:59 by sydfeng |
| HASS试验对CDR的PPM容忍度要求 | sydfeng | 1141/0 | 2015-04-19 12:17:36 by sydfeng |
| 数据采集卡的实现！！！ | 09121981 | 920/0 | 2015-04-19 11:25:26 by 09121981 |
| Transceiver对电源文波噪声的要求 | 09121981 | 863/0 | 2015-04-19 11:24:39 by 09121981 |
| 求助：ERROR:Place:864 - Incompatible IOB's are locked to the same bank 3 | toeflsieasy | 2389/0 | 2015-04-19 11:22:59 by toeflsieasy |
| 如何选择合适的FPGA千兆位收发器？ | toeflsieasy | 1001/0 | 2015-04-19 11:21:26 by toeflsieasy |
| 求助：关于应用笔记xapp224_data recovery | toeflsieasy | 1249/0 | 2015-04-19 11:20:00 by toeflsieasy |
| DSO “comparo”彰显先进的Smarter System | SCOFEEL | 1058/0 | 2015-04-18 23:57:48 by SCOFEEL |
| 回到未来：用图形化方法快速实现复杂的SoC设计 | iamacb1 | 1055/0 | 2015-04-18 23:53:21 by iamacb1 |
| 打造安全的嵌入式系统至关重要 | iamacb1 | 910/0 | 2015-04-18 23:47:42 by iamacb1 |
| 关于V5器件差分接口的一些疑问？ | iamacb1 | 923/0 | 2015-04-18 23:46:42 by iamacb1 |
| 怎么申请 调试版本 以太网络license | a6251356 | 857/0 | 2015-04-18 00:07:57 by a6251356 |
| 使用XILINX FPGA实现的SATA硬盘控制和高速存储 | muzhen2000 | 1007/0 | 2015-04-18 00:05:25 by muzhen2000 |
| 问题求助？Verilog例化ODDR2时报错 | muzhen2000 | 1517/0 | 2015-04-17 23:25:16 by muzhen2000 |
| lwip在xc3s700an上应用时只使用BRAM资源是否足够 | muzhen2000 | 1074/0 | 2015-04-17 23:24:17 by muzhen2000 |
| [求助]Master and Slave R/W address problem .About the three of Processing System(P | muzhen2000 | 1189/0 | 2015-04-17 23:22:43 by muzhen2000 |
| 怎么把用户逻辑V文件翻译成FPGA内部原件的V文件？？？ | 2007zoz | 1014/0 | 2015-04-17 23:21:28 by 2007zoz |
| 求助：关于EDK 下利用LWIP实现双网口 | 2007zoz | 1152/0 | 2015-04-17 23:19:58 by 2007zoz |
| 关于使用clocking wizard 的询问？ | 2007zoz | 1268/0 | 2015-04-17 23:18:39 by 2007zoz |
| where can find the third part programmer qualified by xilinx liset | 2007zoz | 1059/0 | 2015-04-17 23:17:35 by 2007zoz |
| Xilinx 推出全新的 FPGA 设计方法培训课程 | 2007zoz | 941/0 | 2015-04-17 23:16:37 by 2007zoz |
| 把握赛灵思FPGA中的主要时钟资源 (作者：Sharad Sinha 新加坡南洋理工大学博士生) | 091217272 | 1550/0 | 2015-04-16 00:15:30 by 091217272 |
| 最新的vertex5 ug190中DCM、PLL的几个时序图难理解！ | 091217272 | 962/0 | 2015-04-16 00:14:26 by 091217272 |
| 请教如何正确给FPGA的输入时钟和输出时钟分配引脚 | 091217272 | 1009/0 | 2015-04-16 00:13:38 by 091217272 |
| 关于比特流下载出错的问题：Device IDCODE不正确，全是0. | abgh668 | 922/0 | 2015-04-16 00:12:29 by abgh668 |